1. Field of the Invention
The present invention relates to a display apparatus that employs light emitting elements arranged in a matrix, and a light emission control method for controlling the display apparatus.
2. Description of the Related Art
Display apparatuses that employ light emitting diodes (LEDs) as light emitting elements have been manufactured. For example, a large display system can be constructed of a plurality of display apparatuses that cooperate with each other. In the case where a display apparatus is constructed in a matrix with m rows and n columns for example, the anode terminals of LEDs that are arranged in each row are connected to corresponding one common line, while the cathode terminals of LEDs that are arranged in each column are connected to corresponding one driving line. The common lines of m rows are cyclically turned ON one by one at a predetermined sub-frame. When one of the common lines is turned ON, each of the driving lines can drive corresponding one of LEDs that are arranged on the one of the common lines, which is turned ON.
In this display apparatus control method, there is a problem that the brightness of light emitting elements that are first driven in each cycle may be smaller as compared with other light emitting elements. The reason is described with reference to FIGS. 7 to 9. FIG. 7A is a plan view schematically showing a display apparatus. FIG. 7B is a plan view schematically showing the display apparatus with the brightness of a row being smaller. FIG. 8 is a timing chart showing the light emission timing of light emitting elements 1 in a conventional display apparatus. The following description describes the case where one cycle is divided into a plurality of frames for displaying one image. The frames are controlled so that one image can be displayed as a whole. FIGS. 9A to 9H are circuit diagrams showing the current flows in the display apparatus in sub-frames 11 to 23 in FIG. 8. FIGS. 9A, 9B, 9C, 9D, 9E, and 9F show the sub-frames 11, 12, 13, 21, 22, and 23, respectively, in the cycle CL1. FIG. 9G shows the state where residual electric charge is stored. FIG. 9H shows the sub-frame 11 in the cycle CL2 or later. In FIGS. 9 A to 9H, light emitting elements 1 shown in black are light emitting elements 1 that emit light at a desired amount of intensity. Current flows are shown by the arrows. Virtual equivalent capacitors CS0 to CS2 that are included as parasitic capacitances in the lines are shown on the driving lines S0 to S2 (hereinafter, S0 to S2 are occasionally referred to as simply lines “S”).
The display apparatus shown in FIGS. 7A and 7B includes a display portion in a matrix with three rows and three columns. Each dot includes an LED as light emitting element. This display apparatus will have the circuit construction states shown in FIGS. 9A to 9H. The display apparatus includes the light emitting elements 1 that are arranged in the matrix with three rows and three columns (totally nine light emitting elements), three common lines C0 to C2 (hereinafter, C0 to C2 are occasionally referred to as simply lines “C”), the three driving lines S0 to S2, a scanning portion 20, and a driving portion 30. Each of the common lines C0 to C2 is connected to the anode terminals of three light emitting elements 1, which are arranged in corresponding one of the three rows. Each of the three driving lines S0 to S2 is connected to the cathode terminals of three light emitting elements 1 that are arranged in corresponding one of the three columns. The common lines C0 to C2 are scanned by the scanning portion 20. The driving portion 30 can draw currents from the driving lines S0 to S2 so that the currents can flow through light emitting elements 1.
FIG. 8 shows the light emission timing chart of the display apparatus. As shown in this chart, the first cycle CL is indicated by CL1. The first cycle CL is first provided to the display apparatus after power is supplied. The second and third cycles are indicated by CL2 and CL3, respectively. Each of CL1 to CL3 is divided into a plurality of frames FM. In the frames, the scanning order of the common lines C is the same order of C0, C1, and C2. The assumed operation is that, in each cycle, all of the light emitting elements are driven at the minimum intensity (the minimum level) only in FM1, and all of the light emitting elements are turned OFF in other frames. That is, the assumed operation is that, in each of the cycles CL1 to CL3, all the light emitting elements emit light at the minimum intensity. In FIG. 8, although it is shown as if the light emitting elements 1 connected to S0, S1, and S2 are driven at the maximum intensity (maximum level) in the sub-frames 11, 12, and 13 in each cycle for ease of illustration, the assumed operation is that the light emitting elements are driven at the minimum intensity (the minimum level) in FM1.
The operation in the cycle CL1 is now described with reference to FIG. 9A. In the sub-frame 11 where the common line C0 to be first scanned is turned ON in the frame FM1, a voltage is applied to the common line C0 by the scanning portion 20, while predetermined currents are drawn by the driving portion 30 through the driving lines S0 to S2. Accordingly, three light emitting elements 1 that are connected to C0 are driven at a desired amount of intensity. Subsequently, in the sub-frame 12, as shown by FIG. 9B, the voltage is applied to the common line C1 by the scanning portion 20, while predetermined currents are drawn by the driving portion 30 through the driving lines S0 to S2. Accordingly, three light emitting elements 1 that are connected to C1 are driven at a desired amount of intensity. Similarly, in the sub-frame 13, as shown in FIG. 9C, three light emitting elements 1 that are connected to C2 are driven at a desired amount of intensity.
After that, in the sub-frame 21 in frame FM2, as shown in FIG. 9D, although the voltage is applied to the common line C0, the driving lines are in the OFF state so that the driving portion 30 does not draw currents. Accordingly, the parasitic capacitances of the lines (S0, S1, and S2) will be charged. Similarly, in the sub-frame 22, as shown in FIG. 9E, although the voltage is applied to the common line C1, the driving portion 30 does not draw currents. Accordingly, the parasitic capacitances of the lines (S0, S1, and S2) will be charged. Similarly, in the sub-frame 23, as shown in FIG. 9F, the parasitic capacitances of the lines (S0, S1, and S2) will be also charged. In this case, since the lines are similarly scanned in the frames, the parasitic capacitances of the lines will be fully charged and cannot be charged anymore as shown in FIG. 9G.
The operation in the cycle CL2 is now described. The light intensity of a light emitting element that is first driven will be smaller in the cycle CL2 as compared with the cycle CL1. That is, as shown by FIG. 9H, since, in the sub-frame 11 in the frame FM1, the voltage is applied to the common line C0 by the scanning portion 20, and predetermined currents are drawn by the driving portion 30 through the driving lines S0 to S2, three light emitting elements 1 that are connected to C0 are driven.
However, since the parasitic capacitances of the driving lines S0 to S2 are charged in the cycle CL1, the amounts of the currents that are drawn by the driving portion through the driving lines S0 to S2 include not only currents that flow in the light emitting elements 1 but also currents from the parasitic capacitances. That is, since the current that actually flows in the light emitting element 1 in the sub-frame 11 decreases by the amount of current that is discharged by the parasitic capacitance relative to the currents in other sub-frames 12 and 13, the light emission amount of the light emitting element 1 that is connected to C0 in the sub-frame of the cycle CL2 will be smaller as compared with other light emitting elements 1 that are connected to C1 and C2. As a result, a so-called “dark line” phenomenon may occur.
In FIG. 8, to show that light emitting elements 1 may be darker in the sub-frames 11 of the cycles CL2 and CL3, the sub-frame blocks indicating that C0 is in the ON state are hatched in the cycles CL2 and CL3. Also, in FIG. 9H, to show that the parasitic capacitances may reduce the amounts of light intensity of light emitting elements 1, these light emitting elements 1 are hatched.
Subsequently, in the sub-frame 12, as shown by FIG. 9B, the voltage is applied to the common line C1 by the scanning portion 20, while predetermined currents are drawn by the driving portion 30 through the driving lines S0 to S2. Since the currents corresponding to the parasitic capacitances have been drawn out by the driving portion 30 in the frame FM1, three light emitting elements 1 that are connected to C1 can be driven at a desired amount of intensity. Similarly, in the sub-frame 13, as shown in FIG. 9C, three light emitting elements 1 that are connected to C2 can be driven at a desired amount of intensity. Since the operation after the sub-frame 21 is similar to the cycle CL1, its description is omitted for the sake of brevity. In addition, after the cycle CL3, similarly, light emitting elements 1 may be darker in the sub-frame 11. Since the reason is the same as CL2, its description is omitted for the sake of brevity.
As stated above, in conventional driving methods, the parasitic capacitances may reduce the amounts of light intensity of light emitting elements. For this reason, there is a problem that the darker light emitting elements may inversely affect the display quality.
See Laid-Open Patent Publication No. JP 2006-147,933 A
The present invention is devised to solve the above problems. It is a main object of the present invention to provide a display apparatus light emission control method and a display apparatus that can prevent that the amount of light intensity of a light emitting element that is first driven in each cycle is smaller than other light emitting elements, and can improve the display quality.